The rate recording system of the present invention is within the field of devices which operate in real time to sense or monitor processes and events, determine a rate of occurrence of the events over predetermined times and record the various rates for future reference.
The particular system of the present invention may be used to sense the occurrence of such events as traffic passage, industrial machinery output, occurrence of given events in hospital care monitoring and in any other situations in statistical processing control wherein significant events are occurring which are desired to be detected and recoded. The system of the present invention senses each particular event involved, translates the event to a binary count and accumulates the events over a predetermined sampling period. At the end of the time interval, the accumulated events, which have been translated to a binary count, are written to a memory and a new sampling period started. The binary expression entered into the memory is thus a rate expression for the particular time interval involved.
The system continues to accumulate successive rate expressions and record them in the memory for a further predetermined total sampling time. At the end of the total sampling period, the respective rate determinations are read from memory and recorded onto a permanent log.
More specifically, the rate recording system of the present invention accumulates the sensed events in a counter or rate accumulator over the predetermined sampling interval. At the end of the sampling interval, which is internally controlled within the system, the count in the rate accumulator is passed to a parallel in-serial out converter.
The memory employed in the rate recording system of the present invention is a dynamic recirculating memory. Immediately preceding the entry of the rate expression into the parallel in-serial out converter, the recirculating memory is placed in the write mode and the rate expression in the converter is shifted into the recirculating memory. Once the rate word has been entered into the memory, the system is returned to the sensing mode for the next sampling interval and the cycle repeated until the total sampling period has been completed.
Each rate word or binary expression is entered into the memory in a serial fashion, i.e. each succeedingly generated and entered rate word follows the preceding rate word in the train of words circulating in the memory. Indexing of the position in the memory of the last entered word is accomplished in accordance with the present invention by the utilization of a memory position counter of capacity equal to that of the memory. The counter is reset to zero upon entry of a rate word and its count is initiated upon entry of the last bit in the rate word. A decoder is then used to follow the count in the memory position counter and provides an index signal each time the count returns to zero indicating one complete circulation of the memory. The index signal may then be used to operate a second counter to accumulate a predetermined number of index signals to establish the sampling interval and also to index the time to intiate writing to the memory.
The rate recording system further includes a counter which counts the number of binary expressions or rate words entered into the memory. After a predetermined number of such expressions have been entered, as determined by the master sampling period desired, the detected count is used to generate a terminate recording signal which initiates the reading of the data from the memory and recording thereof.
Output from the memory is controlled for first in-first out recording. This is accomplished by creating the terminate recording signal simultaneously with the index signal to establish the position in the memory of the last recorded bit. Thereafter, the count in the memory position counter is decoded at a count representative of the difference between the memory capacity and the total number of bits entered to generate a read signal which occurs at the appearance of the first entered bit.
The binary rate expressions in the memory are serially read from the memory to a serial to parallel output data register. As each word fills the output data register, it is passed in parallel through data gates to a printer to print the particular rate expression. Controls are generated internally within the system to control the output register and printer to accept successively read out words. In accordance with the present invention, the print out may be both a numeric expression of the rate and a bar graph representative of the rate.
The rate recording system counts the number of words exited from the memory. When the number of rate expressions exited from the memory equals that previously entered, the system is returned to the rate accumulate-record mode.